Commit Graph

6 Commits

Author SHA1 Message Date
alro65 ad4c4581b6 fix(spice): corregir errores LTspice en buck chain y output stage
1_buck_chain.cir:
- RL1 creaba nodo flotante V5V_AFTER_L sin retorno
- Reemplazado por parametro Rser=0.051 en L1 (soporte nativo LTspice)

2_output_stage.cir:
- Gcoll con VALUE={} no es sintaxis valida para G-source en LTspice
  → convertido a B-source: Bcoll GATE_Q1 EMITTER I={MAX(0, 1.0*I(Dled))}
- .net V(out1) VLOAD → directiva invalida en este contexto, eliminada
- .meas V(out1) → nodo inexistente, corregido a V(drain_q1)

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
2026-05-23 00:30:24 -04:00
alro65 78a58d1b53 fix: remove invalid .connect directive in output_stage.cir — use shared node name GATE_Q1 2026-05-22 23:27:21 -04:00
alro65 b82ed400bc feat: BNO085 IMU integration — SPICE + simulator yaw rate feed-forward
SPICE (6_bno085_imu.cir):
  - BNO085 power supply with 10uF + 100nF decoupling on VDD
  - Power-on reset RC circuit (R=10K, C=1uF, tau=10ms → deasserts at ~12ms)
  - I2C Fast Mode 400kHz bus: 4.7K pull-ups, 50pF bus capacitance model
  - Full I2C transaction: START + address 0x4A + R/W + BNO085 ACK + STOP
  - INT pin (open-drain, 10K pull-up, 100Hz interrupt simulation)
  - .meas directives: reset timing, SCL rise time, VDD stability

Simulator (esp32_sim.py):
  - SimSnapshot.bno085_yaw_rate_dps field added
  - _bno085_enabled / _bno085_noise_std_dps / _bno085_yaw_rate_dps state
  - enable_bno085(noise_std_dps=0.02) public method
  - disable_bno085() public method
  - _run_physics: samples gyro at 50Hz with Gaussian noise model
  - _run_outer_loop: uses BNO085 yaw rate for rot_ff_term when enabled
    (replaces NMEA-derived ROT — lower latency ~4ms vs ~100-200ms)

Usage:
  sim.enable_bno085()          # activate gyro feed-forward
  sim.enable_bno085(noise_std_dps=0.014)  # with BNO085 spec noise

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
2026-05-22 22:46:16 -04:00
alro65 3b36f178aa fix: update analog input SPICE to reflect corrected 100K+27K resistor values
All analog ports (IN-BAT, IN-WATER, IN-OILP, IN-RPM) now use R_high=100K,
R_low=27K — unified design confirmed in schematic. Updated .param values,
voltage divider netlist, verification comments, and design notes.

Vout @ 14.4V (alternator) = 3.06V — just at the ADC limit, correct.
Vout @ 15.5V = 3.30V — absolute maximum safe input voltage.
Filter fc = 747 Hz with 100K||27K and 10nF.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
2026-05-22 10:19:24 -04:00
alro65 210c44341f feat: LTspice RS-485 / NMEA 0183 interface simulation (SN65HVD1781)
Simulates the full RS-485 half-duplex channel on the ESP32+CAN+RS485 board:
  - SN65HVD1781 behavioral driver/receiver (3.3V native, 32 unit loads)
  - Half-duplex direction control via DE/RE GPIO4
  - 560Ω bias resistors keeping bus HIGH during idle (NMEA 0183 failsafe)
  - 120Ω termination at both ends of a 10m T-line model (Zo=120, Td=50ns)
  - Transmits ASCII 'G' (0x47) at 4800 bps — one complete NMEA character
  - Second node as passive 12kΩ unit-load receiver
  - .meas directives verify Vdiff > ±200mV (RS-485 spec) in both polarities

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
2026-05-22 10:13:16 -04:00
alro65 fa8a65f687 feat: LTspice SPICE netlists for all hardware subcircuits
Four .cir behavioral simulations ready to open in LTspice via File→Open:
  1_buck_chain.cir      — dual MP2338 12V→5V→3.3V, verifies Rfb math + soft-start
  2_output_stage.cir    — PC817 + IRLML6344 isolated output (inverted logic confirmed)
  3_analog_input.cir    — analog input conditioning; flags ADC overvoltage on IN-BAT/WATER/OILP
  4_nmea2000_can.cir    — MCP2562T CAN transceiver, two-node NMEA2000 bus, T-line model

CRITICAL finding in 3_analog_input.cir: R_high=10K + R_low=15K gives 4.3V
at ESP32 ADC when measuring a 12V battery — exceeds 3.3V limit. Fix: use
R_high=100K (same as IN-RPM, which is correctly designed at 3.06V @ 14.4V).

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
2026-05-22 09:59:50 -04:00