alro65
fa8a65f687
Four .cir behavioral simulations ready to open in LTspice via File→Open: 1_buck_chain.cir — dual MP2338 12V→5V→3.3V, verifies Rfb math + soft-start 2_output_stage.cir — PC817 + IRLML6344 isolated output (inverted logic confirmed) 3_analog_input.cir — analog input conditioning; flags ADC overvoltage on IN-BAT/WATER/OILP 4_nmea2000_can.cir — MCP2562T CAN transceiver, two-node NMEA2000 bus, T-line model CRITICAL finding in 3_analog_input.cir: R_high=10K + R_low=15K gives 4.3V at ESP32 ADC when measuring a 12V battery — exceeds 3.3V limit. Fix: use R_high=100K (same as IN-RPM, which is correctly designed at 3.06V @ 14.4V). Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
151 lines
5.6 KiB
Plaintext
151 lines
5.6 KiB
Plaintext
* =======================================================================
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* AR-Autopilot — Cadena de Alimentacion: 12V → 5V → 3.3V
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* Archivo: 1_buck_chain.cir
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* Tarjetas: Modulo ESP32+CAN+RS485 / Modulo ESP32+CAN (nodo compacto)
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*
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* COMO USAR EN LTSPICE:
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* File → Open → seleccionar este .cir
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* Run (boton Play) → ya configurado para .tran 50ms
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* Probes utiles:
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* V(v5v) → tension 5V de salida
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* V(v33) → tension 3.3V de salida
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* I(Rload5) → corriente consumida a 5V
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* I(Rload33)→ corriente consumida a 3.3V
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*
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* MODELO: Average behavioural (no switching). Captura correctamente:
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* - Tension DC de salida (verificacion de Rfb)
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* - Rampa de arranque (soft-start ~2ms)
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* - Respuesta a escalon de carga
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* - Rizado de salida (via ESR del condensador)
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* =======================================================================
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.title AR-Autopilot Buck Chain 12V-5V-3V3
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* -----------------------------------------------------------------------
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* PROTECCION DE ENTRADA 12V
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* -----------------------------------------------------------------------
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* Fusible 1812L125_16DR: 1.25A / 16V — modelado como resistencia serie
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* (en SPICE el fusible no se funde, pero RSer=0.1 Ohm representa la caida)
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* TVS SM6T24A: Vclamp=24V, absorbe load dump marino (hasta 45V transitorio)
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* Para simular el TVS activo, cambiar Vin a PULSE(12 45 10m 1u 1u 1m 100m)
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Vin VIN_RAW GND PULSE(0 12 0 500u 500u 200m 500m)
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Rfuse VIN_RAW VIN_FUSED 0.1
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* Catodo Anodo modelo
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DTVS VIN_FUSED GND DTVS_SM6T24A
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.model DTVS_SM6T24A D(Ron=0.05 Vfwd=24 epsilon=0.5 Ilimit=25)
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* -----------------------------------------------------------------------
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* ETAPA 1: Buck 12V → 5V (MP2338, L=6.8uH, Cout=44uF)
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* -----------------------------------------------------------------------
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* Calculo Vfb: Vout = 0.8V * (1 + R47/R45) = 0.8*(1+52.3k/10k) = 4.984V ≈ 5V
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* Frecuencia de conmutacion: 1.4 MHz
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* Corriente ripple inductor: dIL = Vout*(1-D)/(L*Fsw)
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* = 5*(1-5/12)/(6.8u*1.4M) = 0.306A pp
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* Condensadores de salida: 2x EMK212BBJ226MGT = 2x22uF = 44uF
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* ESR tipico a 1MHz: ~10mOhm por condensador → 5mOhm en paralelo
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* Fuente behavioural — modelo promedio del buck MP2338
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* La rampa de 2ms emula el soft-start interno del IC
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Ebuck1 V5V_IDEAL GND VALUE={
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+ IF( V(VIN_FUSED) > 4.5,
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+ MIN(5.0 , V(VIN_FUSED) * (1 - EXP(-TIME/0.002)) * (5.0/12.0) * (12.0/V(VIN_FUSED)) ),
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+ 0 ) }
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* Resistencia de salida interna (modela perdidas del buck: DCR+RDS_on)
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Rbuck1 V5V_IDEAL V5V_SW 0.05
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* Inductor de salida real: L2 = DRA74-6R8-R (6.8uH, DCR=51mOhm)
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L1 V5V_SW V5V 6.8u
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.ic V(V5V)=0
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* Resistencia serie del inductor (DCR)
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RL1 V5V_SW V5V_AFTER_L 0.051
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* (el inductor ya incluye series resistance internamente, pero LTspice
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* permite separarlo para mejor visualizacion)
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* Condensadores de salida — 2x 22uF en paralelo
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* ESR de EMK212BBJ226MGT a 1MHz: ~10mOhm. En paralelo = 5mOhm
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Cout1a V5V GND 22u IC=0
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.param ESR_emk=0.01
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Resr1a V5V COUT1A_NODE 0.01
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Cout1b COUT1A_NODE GND 22u IC=0
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* Resistencias de feedback (para referencia — no afectan el modelo behavioural)
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* pero verifican el calculo: Vout = 0.8*(1+R47/R45)
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R47 V5V VFB1 52.3k
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R45 VFB1 GND 10k
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* Vfb1 deberia estar en ~0.8V cuando Vout=5V:
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* Vfb1 = 5V * R45/(R47+R45) = 5 * 10k/62.3k = 0.803V ✓
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* Carga de prueba a 5V
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* ESP32 DevKit + MCP2562T + SN65HVD1781 ≈ 200mA total
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* 5V / 200mA = 25 Ohm (carga nominal)
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* Para simular escalon de carga: PULSE(25 12.5 10m 1u 1u 5m 50m)
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Rload5 V5V GND 25
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* Condensador de bypass junto al conector
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Cbypass5 V5V GND 100n
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* -----------------------------------------------------------------------
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* ETAPA 2: Buck 5V → 3.3V (MP2338, L=4.7uH, Cout=44uF)
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* -----------------------------------------------------------------------
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* Calculo Vfb: Vout = 0.8V * (1 + R44/R42) = 0.8*(1+31.6k/10k) = 3.328V ≈ 3.3V
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* Corriente ripple: dIL = 3.3*(1-3.3/5)/(4.7u*1.4M) = 0.171A pp
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Ebuck2 V33_IDEAL GND VALUE={
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+ IF( V(V5V) > 3.5,
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+ MIN(3.3 , V(V5V) * (1 - EXP(-(TIME-0.001)/0.002)) * (3.3/5.0) * (5.0/V(V5V)) ),
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+ 0 ) }
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Rbuck2 V33_IDEAL V33_SW 0.04
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* Inductor: L3 = NRS5010T4R7NMGF (4.7uH, DCR=28mOhm, Isat=4.8A)
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L2 V33_SW V33 4.7u
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.ic V(V33)=0
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* Condensadores de salida — 2x 22uF
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Cout2a V33 GND 22u IC=0
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Cout2b V33 GND 22u IC=0
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* Resistencias de feedback
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* Vout = 0.8*(1+R44/R42) = 0.8*(1+31.6k/10k) = 3.328V
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R44 V33 VFB2 31.6k
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R42 VFB2 GND 10k
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* Carga de prueba a 3.3V
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* ESP32 activo consumo tipico: 80mA @ 3.3V → 41 Ohm
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* Picos en TX WiFi: 350mA → 9.4 Ohm
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* Carga nominal para prueba:
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Rload33 V33 GND 41
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Cbypass33 V33 GND 100n
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* -----------------------------------------------------------------------
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* DIRECTIVAS DE SIMULACION
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* -----------------------------------------------------------------------
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* Analisis transitorio: 50ms total, paso maximo 1us
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* Permite ver:
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* - Rampa de arranque (0-5ms)
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* - Estado estable (10-50ms)
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* - Rizado de salida (zoom a estado estable)
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.tran 0 50m 0 1u
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* Opciones de convergencia para fuentes behaviorales
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.options reltol=0.001 abstol=1n vntol=1m
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* -----------------------------------------------------------------------
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* VALORES ESPERADOS (verificar con probes)
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* -----------------------------------------------------------------------
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* V(v5v) en estado estable: 4.95V - 5.05V (tolerancia ±1% del MP2338)
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* V(v33) en estado estable: 3.267V - 3.333V
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* V(vfb1) en estado estable: ~0.803V
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* V(vfb2) en estado estable: ~0.797V
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* I(Rload5) en estado estable: ~200mA
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* I(Rload33) en estado estable: ~80mA
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* Tiempo de arranque (10%-90%): ~2-4ms por etapa
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.backanno
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.end
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