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fix(spice): corregir errores LTspice en buck chain y output stage

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1_buck_chain.cir:
- RL1 creaba nodo flotante V5V_AFTER_L sin retorno
- Reemplazado por parametro Rser=0.051 en L1 (soporte nativo LTspice)

2_output_stage.cir:
- Gcoll con VALUE={} no es sintaxis valida para G-source en LTspice
  → convertido a B-source: Bcoll GATE_Q1 EMITTER I={MAX(0, 1.0*I(Dled))}
- .net V(out1) VLOAD → directiva invalida en este contexto, eliminada
- .meas V(out1) → nodo inexistente, corregido a V(drain_q1)

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
This commit is contained in:
Alvaro Enrique Romero Donado
2026-05-23 00:30:24 -04:00
parent 78a58d1b53
commit ad4c4581b6
2 changed files with 5 additions and 9 deletions
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tools/spice/1_buck_chain.cir
+2 -6
View File
@@ -57,14 +57,10 @@ Ebuck1 V5V_IDEAL GND VALUE={
Rbuck1 V5V_IDEAL V5V_SW 0.05
* Inductor de salida real: L2 = DRA74-6R8-R (6.8uH, DCR=51mOhm)
L1 V5V_SW V5V 6.8u
* DCR modelado con Rser= (parametro interno de LTspice) — evita nodo flotante
L1 V5V_SW V5V 6.8u Rser=0.051
.ic V(V5V)=0
* Resistencia serie del inductor (DCR)
RL1 V5V_SW V5V_AFTER_L 0.051
* (el inductor ya incluye series resistance internamente, pero LTspice
* permite separarlo para mejor visualizacion)
* Condensadores de salida — 2x 22uF en paralelo
* ESR de EMK212BBJ226MGT a 1MHz: ~10mOhm. En paralelo = 5mOhm
Cout1a V5V GND 22u IC=0
tools/spice/2_output_stage.cir
+3 -3
View File
@@ -67,7 +67,7 @@ Rcathode CATHODE_LED GND 1 ; resistencia de retorno (cableado)
* Lado transistor (modelado como VCCS proporcional a corriente LED)
* Gcollector: corriente de colector = CTR * corriente LED
* CTR = 100% minimo garantizado a IF=5mA
Gcoll GATE_Q1 EMITTER VALUE={MAX(0, 1.0 * I(Dled))}
Bcoll GATE_Q1 EMITTER I={MAX(0, 1.0 * I(Dled))}
Remit EMITTER GND 0.1 ; Vce_sat ~ 0.1V a Ic<5mA
* -----------------------------------------------------------------------
@@ -132,13 +132,13 @@ Rload_out VLOAD DRAIN_Q1 120 ; 12V / 120Ω = 100mA (ej: LED + rele)
* -----------------------------------------------------------------------
.meas TRAN Pdiss_R9 AVG {I(Rdrive)^2 * 332} FROM 60m TO 100m
.meas TRAN I_led_avg AVG {ABS(I(Dled))} FROM 60m TO 100m
.meas TRAN Vout_on AVG V(out1) FROM 60m TO 100m
.meas TRAN Vout_on AVG V(drain_q1) FROM 60m TO 100m
.meas TRAN Vgs_on AVG V(gate_q1) FROM 60m TO 100m
* -----------------------------------------------------------------------
* NODO DE SALIDA
* -----------------------------------------------------------------------
.net V(out1) VLOAD
* Probe: V(drain_q1) para ver la tension de salida al load
* -----------------------------------------------------------------------
* DIRECTIVAS DE SIMULACION